1. Field of the Invention
The present invention relates generally to a communication system. In particular, the present invention relates to a method and apparatus for communicating transmission/reception data of a codec interface that processes voice and audio information in a mobile communication chip.
2. Description of the Related Art
Generally, a wideband stereo codec includes an analog-to-digital converter (ADC) for converting voice and audio information, that is an analog signal, received at a reception apparatus (for example, terminal) in a mobile communication system, into a digital signal, and a digital-to-analog converter (DAC) for converting a digital signal into an analog signal to output voice and audio signal. The wideband stereo codec further includes an apparatus for performing coding/decoding on the voice and audio information.
The wideband stereo codec is connected to a codec interface, and exchanges transmission/reception data with other hardware blocks prepared in the reception apparatus. The codec interface includes a transmission First-In-First-Out (FIFO) memory for storing transmission data and a reception FIFO memory for storing received data, and exchanges data associated with voice and audio information with the wideband stereo codec.
In this context, FIG. 1 is a diagram illustrating a conventional FIFO structure that includes capacity-fixed transmission FIFO memory and reception FIFO memory and exchanges data with a wideband stereo codec connected thereto.
Referring to FIG. 1, the FIFO structure of the conventional codec interface 130 separately uses a transmission FIFO memory 135 and a reception FIFO memory 140. The codec interface 130 performs interfacing with a wideband stereo codec 115 via the transmission FIFO memory 135 and the reception FIFO memory 140 having a predetermined size. That is, the transmission FIFO memory 135 and the reception FIFO memory 140 are separated from each other by hardware. In Application Specific Integrated Circuit (ASIC) design, the transmission FIFO memory 135 and the reception FIFO memory 140 perform an interfacing operation using predetermined memory capacity.
In other words, the codec interface 130 adopts a scheme of controlling flow of transmission data using the transmission FIFO memory 135, and controlling flow of reception data using the reception FIFO memory 140. A description will now be made of a procedure for exchanging voice and audio information between the wideband stereo codec 115 and the codec interface 130.
In a voice and audio information transmission process, generated voice and audio information is input to the transmission FIFO memory 135 in the codec interface 130 via a bus 145 which is an information delivery path between peripheral hardware chips. The transmission FIFO memory 135 sequentially stores the sequentially received voice and audio information. The voice and audio information stored in the transmission FIFO memory 135 is sequentially delivered to the wideband stereo codec 115, and converted into an analog voice and audio signal by a DAC 120. Thereafter, the analog voice and audio signal is output over the air via a speaker 105.
In a voice and audio information reception process, an analog signal input via a microphone 110 is converted into digital data by an ADC 125 in the wideband stereo codec 115. The reception FIFO memory 140 in the codec interface 130 sequentially stores the sequentially received digital data. The digital voice and audio information is delivered to other hardware devices via the bus 145.
As described above, the conventional codec interface 130 has a fixed size, and transmits/receives voice and audio information using the transmission FIFO memory 135 and the reception FIFO memory 140, which are separated by hardware. That is, the codec interface 130 includes at least two FIFO memories of the transmission FIFO memory 135 and the reception FIFO memory 140. Therefore, the conventional mobile communication chip needs at least two Dual-Port Random Access Memories (DPRAMs).
Generally, in a semiconductor process, as the number of memories increases, a Design For Test (DFT) logic increases in size. This means an increase in layout and wiring efforts. Therefore, the need for the two separate DPRAMs causes unnecessary processing delay.
In addition, because the conventional codec interface unconditionally separately uses the transmission FIFO memory with predetermined capacity and the reception FIFO memory with predetermined capacity, it has a predetermined size in terms of hardware.
However, because the conventional codec interface has only the transmission FIFO memory or reception FIFO memory with predetermined capacity, when there is a large amount of voice and audio information, the transmission FIFO memory stores the information as much as the predetermined capacity and then must waits for memory to become available in order to continue processing.